This invention is generally directed to finite state machines implemented in a microprocessor having memory in which logical expressions are stored. This invention is specifically direct to such an implementation wherein specially identified logical vectors are stored in an index format to minimize the execution time required to compare the indexed vector with another vector.
As used herein, a finite state machine refers to a sequential system in which input parameters determine the state of operation of the machine. An implementation of a finite state machine is described in U.S. Pat. No. 5,301,100, entitled "Method of an Apparatus for Constructing a Control System and Control System Created Thereby", filed Apr. 27, 1991. This Patent describes a logic table for implementing the finite state machine in which a specific organization of data represents application logic conditions expressed utilizing logical AND and OR operators. FIGS. 1-7 in the present application describe aspects of such a prior art finite state machine implementation. FIG. 4 of the present application illustrates a finite state machine model as contemplated by this prior art.
In the finite state machine model, in accordance with the above-referenced prior art, a change of input parameters is required following a change of state transition before a test is made to determine if output actions are required in response to predetermined input parameter conditions. In certain applications it is desirable to be able to process such input conditions although a change in input parameters has not occurred since the change of state. One way of inducing such input parameter testing is to utilize an additional input parameter not related to the sinced input parameters which can be toggled solely to cause a reevaluation of input parameters. Such an input can be considered a "kicker" in order to initiate an action by the prior art finite state machine. The use of such an input kicker is undesirable in that it adds to the number of inputs and must be initiated at an appropriate time relative to the state of the finite state machine in order to be effective. Thus, there exists a need for an improved finite state machine model which overcomes the afore-referenced deficiency.
In the finite state machine model in accordance with the above-referenced prior art, a plurality of "AND" vectors are stored in an application logic table and define the processing steps implemented by the general flow of the state machine. Input parameters are represented by an input vector having a given bit length. The AND vectors are each of the same length as the input vector and are compared with the input vector on a bit-by-bit basis to make logical determinations in accordance with the state machine.
For a number of applications, the AND vectors of the prior art implementation consist of a single set bit. Thus, the combination of all other bits in such an AND vector with the input vector are unnecessary in that such comparisons can not yield a TRUE result. The comparison with AND vectors with the input vector on a bit-by-bit basis requires a number of execution cycles. Thus, there exists a need to enhance the execution speed by minimizing unnecessary bit-by-bit comparisons.